Updated 2014-05-13 05:49:57 by pooryorick

Page idea Theo Verelst, please add more data / links

[VHDL] (an initialism for VHSIC Hardware Design Language) is a digital electronics definition language, it is used to make hardware with or to program computer circuits which have flexible structure such as fpga's or Xilinx type of chips. Another HDL with large mind-share is Verilog.

This is to remind me to when I get to the possibility of writing some example tcl generator scripts with an actual Xilinx coolrunner Chip and devenv around to examplify the possible use of tcl and also bwise to automatically generate computer circuits which then via vhdl can be actualized. I've made moderate complexity circuitry which works, and there are applications where it is handy to have a tcl in the loop, and certainly to have a general enough graph editor around.

A (small) xilinx or altera CPLD (Complex Programmable Logic Device) could be used as an alternative to the circuitry in the wiki page LED display driven by the parallel port under tcl control and other circuits connected with Tcl/Tk programs. There are about $50 (50 euro) kits with quite capable devices on a board with connectors and a progammer environment available for web purchase, they work neat.

The main link with Tcl ? Tcl got into existence as Tool Command Language, IIRC even as chip design related. Lots of scripting is desirable for serious computer aided circuit design, as well as an serious interpreted language with UI possibilities. Amoung tons of books and IT related activities something people seem to forget.

And there is a parallel with a functional readable computer language, which defines programs/processes.

2004-11-01 VI It's used heavily in the chip design (EDA tools in general) area. The heavy hitters : Mentor Graphics (simulation, testing), Synopsys (synthesis, simulation, testing, ...), Cadence (synthesis, simulation, layout), Magma (synthesis, layout), use it for most of their tools. My company does have many Tk based tools that use Tcl to (auto-)generate both VHDL and Verilog - called HDL in general. I'm not related to any of those companies but often wish I had to pay a lot less for their tools.


http://www.emlabs.info/ Universities and Research Groups (embedded systems)

http://www.opencores.org/ Open Source cores (logic designs)

clement: Hello I am looking for a TCL package that would be able to indent a VHDL code (that is already generated by a TCL script but not indented). Do you know some ?